Sample Verilog Serial RX source code.
module SerialRx(RxClkX8, RxD, RxRst, RxDoutValid, FrameError, RxDout, ParError);
parameter ONE = 1;
parameter BITS_PER_BYTE = 8;
parameter THREE = 3;
parameter BITS_PER_BAUD_M1 = 10;
// Diagram Input Ports
input RxClkX8;
input RxD;
input RxRst;
// Diagram Output Ports
output RxDoutValid;
output FrameError;
output [BITS_PER_BYTE-1:0] RxDout;
output ParError;
// Object Output Declarations
reg [BITS_PER_BAUD_M1-1:0] Q_ShiftReg;
reg [THREE-1:0] Q_BitSync;
reg Qlsb_ShiftReg, Qtc_BitSync, Q_RxDReg, Yerror_Parity1;
// Object Input Declarations
wire [THREE-1:0] Dload_BitSync;
wire SyncLoad_BitSync;
wire [BITS_PER_BYTE-1:0] D_Parity1;
wire Parity_Parity1;
// Output Port Assignments
assign RxDoutValid = ! Q_ShiftReg[0] && Qtc_BitSync ;
assign FrameError = ~ Q_RxDReg ;
assign RxDout = Q_ShiftReg[8:1] ;
assign ParError = Yerror_Parity1 ;
// Object Input Assignments
assign Dload_BitSync = 3'b110 ;
assign SyncLoad_BitSync = Q_RxDReg ^ RxD ;
assign D_Parity1 = Q_ShiftReg[8:1] ;
assign Parity_Parity1 = Q_ShiftReg[9] ;
//*****************************************************************************
// Object:ShiftReg Class:ShiftRegister
//***************************** Tagged Values**********************************
// WIDTH = 10 Edge = Rising Direction = Right
// DataOut = Parallel ShiftEn = Used Clear = UnUsed
// Set = Sync Load = UnUsed Rev = 1.07;
//*****************************************************************************
//Shift Reg with full baud - Low (space) at msb flags end of baud
always @ ( posedge RxClkX8 ) begin
if ( (!Qlsb_ShiftReg && Qtc_BitSync) || RxRst ) begin
Q_ShiftReg <= ~0 ;
end else if ( Qtc_BitSync ) begin
Q_ShiftReg <= { Q_RxDReg , Q_ShiftReg [ BITS_PER_BAUD_M1 -1:1]} ;
end // endif
end // always
always @* begin
Qlsb_ShiftReg <= Q_ShiftReg [0] ;
end // always @()
//
//*****************************************************************************
// Object:BitSync Class:Counter
//***************************** Tagged Values**********************************
// WIDTH = 3 MODULUS = UnUsed GrayOut = UnUsed
// Edge = Rising Direction = Up CountEn = UnUsed
// Clear = UnUsed Set = UnUsed Load = Sync
// TerminalCount = Sync Rev = 1.10;
//*****************************************************************************
//TC flags center of bit cycle to clock data - Syncs on any RxD transition
parameter [ THREE -1:0] ones_BitSync = ~0 ;
always @ ( posedge RxClkX8 ) begin
if ( SyncLoad_BitSync ) begin
Q_BitSync <= Dload_BitSync ;
Qtc_BitSync <= Dload_BitSync == ones_BitSync ;
end else begin
Q_BitSync <= Q_BitSync +1 ;
Qtc_BitSync <= Q_BitSync == ( ones_BitSync -1) ;
end // endif
end // always
//
//*****************************************************************************
// Object:RxDReg Class:Register
//***************************** Tagged Values**********************************
// WIDTH = 1 Edge = Rising ClockEn = UnUsed
// Clear = UnUsed Set = UnUsed Load = UnUsed
// Rev = 1.02;
//*****************************************************************************
//Delays RxD by 1 RxClkX8 cycle
always @ ( posedge RxClkX8 ) begin
Q_RxDReg <= RxD ;
end // always
//
//*****************************************************************************
// Object:Parity1 Class:Parity
//***************************** Tagged Values**********************************
// WIDTH = 8 Function = Checker Parity = Odd
// Registered = No Enable = UnUsed Rev = 1.07;
//*****************************************************************************
always @* begin
Yerror_Parity1 <= ~^{ D_Parity1 , Parity_Parity1 } ;
end // always @()
endmodule