Sample Vhdl Serial TX source code.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SerialTx is
generic (BITS_PER_BAUD : integer := 11;
BITS_PER_BYTE : integer := 8;
BITS_PER_BAUD_M1 : integer := 10;
FOUR : integer := 4 );
port (-- Diagram Input Ports
TxDin : in unsigned (BITS_PER_BYTE-1 downto 0 );
TxDWr : in std_logic;
TxRst : in std_logic;
TxClk : in std_logic;
-- Diagram Output Ports
TxRdy : out std_logic;
TxD : out std_logic );
end entity SerialTx;
architecture Behavioral of SerialTx is
-- Object Output Declarations
signal Q_BaudCtr : unsigned (FOUR-1 downto 0 );
signal Qlsb_ShiftReg, Ytc_BaudCtr, Yparity_Parity1 : std_logic;
-- Object Input Declarations
signal MSBin_ShiftReg : std_logic ;
signal D_ShiftReg : unsigned (BITS_PER_BAUD_M1-1 downto 0 );
-- Local Variable Declarations
signal Q_ShiftReg : unsigned ( BITS_PER_BAUD_M1 -1 downto 0) ;
constant maxCount_BaudCtr : unsigned ( FOUR -1 downto 0) := to_unsigned (
BITS_PER_BAUD - 1, FOUR ) ;
constant ones_BaudCtr : unsigned ( FOUR -1 downto 0) := ( OTHERS =>'1') ;
constant zeros_BaudCtr : unsigned ( FOUR -1 downto 0) := ( OTHERS =>'0') ;
constant tcount_BaudCtr : unsigned ( FOUR -1 downto 0) := ( OTHERS =>'0') ;
-- Function Declarations
function rxor_Parity1 ( ina_Parity1 : unsigned ) return std_logic is
variable ret_Parity1 : std_logic ;
begin
for iterator in 0 to BITS_PER_BYTE -1 loop
if ( iterator = 0) then
ret_Parity1 := ina_Parity1 (0) ;
else
ret_Parity1 := ret_Parity1 XOR ina_Parity1 ( iterator ) ;
end if;
end loop ;
return ret_Parity1 ;
end function;
begin
-- Output Port Assignments
TxRdy <= Ytc_BaudCtr ;
TxD <= Qlsb_ShiftReg ;
-- Object Input Assignments
MSBin_ShiftReg <= '1' ;
D_ShiftReg <= Yparity_Parity1 & TxDin & '0' ;
--*****************************************************************************
-- Object:ShiftReg Class:ShiftRegister
--***************************** Tagged Values**********************************
-- WIDTH = 10 Edge = Rising Direction = Right
-- DataOut = Serial ShiftEn = UnUsed Clear = UnUsed
-- Set = Sync Load = Sync Rev = 1.07;
--*****************************************************************************
process ( TxClk )
begin
if rising_edge ( TxClk ) then
if ( TxRst ='1') then
Q_ShiftReg <= ( OTHERS =>'1') ;
elsif ( TxDWr ='1') then
Q_ShiftReg <= D_ShiftReg ;
else
Q_ShiftReg <= MSBin_ShiftReg & Q_ShiftReg ( BITS_PER_BAUD_M1 -1 downto 1) ;
end if;
end if;
end process;
Qlsb_ShiftReg <= Q_ShiftReg (0) ;
--*****************************************************************************
-- Object:BaudCtr Class:Counter
--***************************** Tagged Values**********************************
-- WIDTH = 4 MODULUS = 11 GrayOut = UnUsed
-- Edge = Rising Direction = Down CountEn = Used
-- Clear = Sync Set = UnUsed Load = UnUsed
-- TerminalCount = Comb Rev = 1.10;
--*****************************************************************************
process ( TxClk )
begin
if rising_edge ( TxClk ) then
if ( TxRst ='1') then
Q_BaudCtr <= ( OTHERS =>'0') ;
elsif ( not Ytc_BaudCtr or TxDWr) then
if ( Q_BaudCtr = zeros_BaudCtr ) then
Q_BaudCtr <= maxCount_BaudCtr ;
else
Q_BaudCtr <= Q_BaudCtr -1 ;
end if;
end if;
end if;
end process;
process ( Q_BaudCtr )
begin
if ( Q_BaudCtr = tcount_BaudCtr ) then
Ytc_BaudCtr <='1';
else
Ytc_BaudCtr <='0';
end if;
end process;
--*****************************************************************************
-- Object:Parity1 Class:Parity
--***************************** Tagged Values**********************************
-- WIDTH = 8 Function = Generator Parity = Odd
-- Registered = No Enable = UnUsed Rev = 1.07;
--*****************************************************************************
Yparity_Parity1 <= not rxor_Parity1 ( TxDin ) ;
end architecture;