Sample Verilog Serial TX source code.
module SerialTx(TxDin, TxDWr, TxRst, TxClk, TxRdy, TxD);
parameter BITS_PER_BAUD = 11;
parameter BITS_PER_BYTE = 8;
parameter BITS_PER_BAUD_M1 = 10;
parameter FOUR = 4;
// Diagram Input Ports
input [BITS_PER_BYTE-1:0] TxDin;
input TxDWr;
input TxRst;
input TxClk;
// Diagram Output Ports
output TxRdy;
output TxD;
// Object Output Declarations
reg [FOUR-1:0] Q_BaudCtr;
reg Qlsb_ShiftReg, Ytc_BaudCtr, Yparity_Parity1;
// Object Input Declarations
wire MSBin_ShiftReg;
wire [BITS_PER_BAUD_M1-1:0] D_ShiftReg;
// Output Port Assignments
assign TxRdy = Ytc_BaudCtr ;
assign TxD = Qlsb_ShiftReg ;
// Object Input Assignments
assign MSBin_ShiftReg = 1'b1 ;
assign D_ShiftReg = {Yparity_Parity1,TxDin,1'b0} ;
//*****************************************************************************
// Object:ShiftReg Class:ShiftRegister
//***************************** Tagged Values**********************************
// WIDTH = 10 Edge = Rising Direction = Right
// DataOut = Serial ShiftEn = UnUsed Clear = UnUsed
// Set = Sync Load = Sync Rev = 1.07;
//*****************************************************************************
reg [ BITS_PER_BAUD_M1 -1:0] Q_ShiftReg ;
always @ ( posedge TxClk ) begin
if ( TxRst ) begin
Q_ShiftReg <= ~0 ;
end else if ( TxDWr ) begin
Q_ShiftReg <= D_ShiftReg ;
end else begin
Q_ShiftReg <= { MSBin_ShiftReg , Q_ShiftReg [ BITS_PER_BAUD_M1 -1:1]} ;
end // endif
end // always
always @* begin
Qlsb_ShiftReg <= Q_ShiftReg [0] ;
end // always @()
//*****************************************************************************
// Object:BaudCtr Class:Counter
//***************************** Tagged Values**********************************
// WIDTH = 4 MODULUS = 11 GrayOut = UnUsed
// Edge = Rising Direction = Down CountEn = Used
// Clear = Sync Set = UnUsed Load = UnUsed
// TerminalCount = Comb Rev = 1.10;
//*****************************************************************************
always @ ( posedge TxClk ) begin
if ( TxRst ) begin
Q_BaudCtr <= 0 ;
end else if ( TxDWr || TxDWr ) begin
if ( Q_BaudCtr == 'b0 ) begin
Q_BaudCtr <= BITS_PER_BAUD -1 ;
end else begin
Q_BaudCtr <= Q_BaudCtr -1 ;
end // endif
end // endif
end // always
always @* begin
if ( Q_BaudCtr == 'b0 ) begin
Ytc_BaudCtr = 1'b1 ;
end else begin
Ytc_BaudCtr = 1'b0 ;
end // endif
end // always
//*****************************************************************************
// Object:Parity1 Class:Parity
//***************************** Tagged Values**********************************
// WIDTH = 8 Function = Generator Parity = Odd
// Registered = No Enable = UnUsed Rev = 1.07;
//*****************************************************************************
always @* begin
Yparity_Parity1 <= ~ (^ TxDin ) ;
end // always @()
endmodule